Re: [v4l-dvb-maintainer] bttv driver questions

[Trent Piepho <xyzzy@xxxxxxxxxxxxx>]

On Wed, 27 Aug 2008, Daniel [iso-8859-1] Glöckner wrote:
> On Mon, Aug 25, 2008 at 08:40:51PM -0400, Andy Walls wrote:
> > On Mon, 2008-08-25 at 14:45 +0200, Jean Delvare wrote:
> > > * Does the bttv driver have anything special to do for full
> > >   resolution frames, that it doesn't have to do for half resolution
> > >   ones? In particular, I wonder if the BT878 DMA engine knows how to
> > >   interlace fields when writing to the memory, or if the bttv driver
> > >   must take care of reordering the fields properly afterwards. I
> > >   suspect the latter.
>
> The driver fills buffers with instructions for the DMA engine, one buffer
> for the top field and one for the bottom field. These instructions tell
> the engine where to write a specific pixel. For interlaced video the
> instructions for the top field write to line 0, 2, 4, ... in memory and for
> the bottom field to line 1, 3, 5, ... .

Keep in mind that _either_ field can be transmitted first.  I.e., in some
cases one first writes lines 1,3,5 then lines 0,2,4.  I'm not sure if bttv
supports both field dominances or not, but I think it does.

> > So with a BT878 latency timer of 32 cycles, a 128 byte burst could be
> > sent as 2 transactions, assuming a maximum target setup time for the
> > host bridge, with a transfer that doesn't hit a modified cache line,
> > assuming transparent arbitration:
> >
> I think worst case for slow targets is more like
>
> 1 addr cycle
> 15 setup cycles (unsure if initial latency includes addr cycle...)
> 1 data cycle
> 7 setup cycles
> 1 data cycle
> 7 setup cycles <-- latency timer of 32 expires, assuming GNT# is deasserted

Isn't the latency timer in units of 250 ns, not PCI cycles?

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